In our prior study of an L-bit priority encoder (PE), a so-calledone-directional-array to two-directional-array conversion method is deployed toturn an L-bit input data into an MxN-bit matrix. Following this, an N-bit PEand an M-bit PE are employed to obtain a row index and column index. Fromthose, the highest priority bit of L-bit input data is achieved. This briefextends our previous work to construct a scalable architecture ofhigh-performance large-sized PEs. An optimum pair of (M, N) and look-aheadsignal are proposed to improve the overall PE performance significantly. Theevaluation is achieved by implementing a variety of PEs whose L varies from4-bit to 4096-bit in 180-nm CMOS technology. According to post-place-and-routesimulation results, at PE size of 64 bits, 256 bits, and 2048 bits theoperating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times,1.5 times, and 1.4 times, as high as state-of-the-art ones.
展开▼
